In existing optimization frameworks, compiler passes are not tightly integrated and often work at cross purposes. In this report we describe an integration framework for the key backend compiler optimizations of register allocation and instruction selection: Register Allocation Aware Instruction Selection (RA²ISE). We discover that the fundamental building block of the RA²ISE framework, register allocation aware tiles (RAATs), introduce significant complexity into the network flow model of register allocation. It is unlikely that efficient and effective solution techniques exist when RAATs are incorporated into the model. We also explore the merits of another component of the RA²ISE framework, feedback driven instruction selection and find that the expected benefits are far outweighed by the necessary costs.

18 pages

Return to: SCS Technical Report Collection
School of Computer Science

This page maintained by [email protected]