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CMU-CS-05-118
Computer Science Department
School of Computer Science, Carnegie Mellon University
CMU-CS-05-118
Optimistic Intra-Transaction Parallelism
on Chip Multiprocessors
Christopher B. Colohan, Anastassia Ailamaki,
J. Gregory Steffan*, Todd C. Mowry
March 2005
CMU-CS-05-118.ps
CMU-CS-05-118.pdf
Keywords: Thread level speculation, TLS, database systems,
chip multiprocessors, OLTP, TPC-C
With the advent of chip multiprocessors, exploiting intra-transaction
parallelism is an attractive way of improving transaction performance.
However, exploiting intra-transaction parallelism in existing database
systems is difficult, for two reasons: first, significant changes are
required to avoid races or conflicts within the DBMS, and second, adding
threads to transactions requires a high level of sophistication from
transaction programmers. In this paper we show how dividing a
transaction into speculative threads solves both
problems---it minimizes
the changes required to the DBMS, and the details of parallelization are
hidden from the transaction programmer. Our technique requires a
limited number of small, localized changes to a subset of the low-level
data structures in the DBMS. Through this method of parallelizing
transactions we can dramatically improve performance: on a simulated
4-processor chip-multiprocessor, we improve the response time by more
than a factor of two when running an OLTP workload.
25 pages
* Department of Electrical & Computer Engineering, University of Toronto,
Ontario, Canada
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